Integrated Circuit (IC) packages, chips (sometimes call die), and other devices have evolved into very dense packaged structures. Semiconductor miniaturization has resulted in the development of very large scale integrated circuit (VLSI) devices with millions of active and passive components. These devices are typically encapsulated in a protective package providing a large number of pin-outs for mounting or interconnection to external circuitry through a carrier substrate such as a printed circuit board or other higher-level packaging.
The semiconductor industry is well over 60 billion dollars a year market. Improved fabrication technologies have lowered cost while increasing functional power thereby revolutionizing the electric marketplace. The ability to put more and more functionality and higher performance is general made possible by repeatedly shrinking feature sizes. However, as the more and more functionality and performance characteristics are included in these chips, the limits of current technologies and methodologies are approached. There are a number of issues and trends that are becoming readily apparent. For example, package temperature issues are exacerbated by a number of factors including static power and lowered junction temperatures due to smaller feature sizes and lowered thresholds. Also, hot spots within the chips are exacerbated by the active elements being buried so deeply beneath the conducting layers and contacts.
In the formation of integrated circuits, a number of active and passive semiconductor devices are formed on each of many die on a wafer, such as silicon. The fabrication technology for integrated circuits has vastly improved yields such that large arrays of electronic circuits on many die are produced on a single semiconductor wafer. In a typical die, two or more silicide layers and up to eight metallization layers, each separated by a dielectric layer, are currently used to interconnect among the active and passive elements to form the individual circuits and to interconnect among those circuits to form the die. They are also used to provide bonding pads at the top of the die. For example, Texas Instruments has a 65 nm process that uses eleven (11) copper conducting layers plus two polysilicide layers for a total of twenty-seven (27) conducting and dielectric layers.
Typical interface schemes for integrated circuit packaging include Pin Grid Array (PGA) Ball Grid Array (BGA), and Land Grid Array (LGA). PGA packages use a two-dimensional array of pins directly connected by soldering or inserted into through-hole pads in a Printed Circuit Board (PCB). BGA packages have a two-dimensional array of conductive pads, such as balls, bumps or pillars, and are mounted by soldering the pads on the package to corresponding surface pads on the mount side of the PCB. LGA packages have a array of metal stubs and are mounted to the PCB in a clamp with a compressible interposer material placed between the package and the PCB.
For illustrative purposes, the description herein will focus somewhat on the most co non package, the BGA. The BGA and pads of the semiconductor die are some connected to the printed circuit board via conductors, either by direct contact in a flip-chip orientation through conductive balls, bumps or pillars or, by intermediate connector elements comprising wire bonds, or TAB (flexible circuit) connections. More commonly they are connected inside a package which in turn is soldered to the PCB. In addition, as ball sizes shrink, they are less tolerant of the already worsening planarity problems.
One of the well-known problems with having the connection balls on the active surface of the die is the planarity required of the die. The problem is compounded as the number of mask levels increase to accommodate the latest demand for processors and memory. The further layers exacerbate the planarity problem and make the die connection more difficult. Another problem associated with the dense packaging is that the fanin/fanout of a given ball is limited to either a single fanin or a single fanout. One of many deleterious effects of this property is that only one element can be placed on a bus unless another delay stage is introduced. Typically, many three state elements are “hung” on a bus, and only one such element is active at any one time. The third state, the high impedance state, of the inactive elements ensures that they neither charge nor discharge the bus.
With respect to the formation of BGA structures, these structures typically require the die to be flipped upside down hence the name “flip chip”. A problem with flipping the chip upside down is that all possibilities of monitoring chip behavior in-situ are eliminated. Integrated circuit (IC) dies typically connect to the substrate within the IC package using either wire bond or Flip-Chip technology. Flip-Chip bonding is normally used for high pin count IC dies, and the pins on the Flip-Chip die are called bump pads. As with the package array technologies, there is a matching pattern of pads on the package substrate. Interconnect on the package substrate is typically used to connect the pads on the substrate (connected directly to the IC die) to the pins, pads, or stubs on the surface of the package that gets inserted, soldered, or pressed to the PCB.
A further problem with using the current flip chip techniques arises from a combination of bringing the interconnects to the top of the die in combination with the large number of layers. The connection to/from the underlying layers must be brought to the top of the die for connection to a connection ball. Current chips have six to eight metallization layers plus two polysilicon layers, and each of these conducting layers is separated from adjacent conducting layers by a dielectric layer. Thus, a signal on the lowest conducting layer may have to go through as many as nine conducting layers and ten dielectric layers, including one on the top surface, in order to reach the top surface and be connected to an interconnect ball.
In order to traverse from each conduction layer through the intervening dielectric layer to connect to an adjacent conduction layer generally requires a stepped via to minimize and avoid step coverage problems. A stepped via is a hole whose cross-section is larger on one end than on the other. It has a contact on both conducting layers, and a short piece of interconnect to route to a via to go to the next upper or lower conduction layer. This process is repeated for each such signal line for each conducting layer until the top is reached. Both the vias and the contacts are considerably larger than the width of the line; thus a considerable area is utilized just for the interconnects to the balls on the top surface of the chip.
It is well-known that as the capacity and speed of many integrated circuit devices, such as dynamic random access memories (DRAMs) have increased, the number of inputs and outputs (I/Os) to/from each die has increased, requiring more numerous and complex external connections thereto and, in some instances, requiring undesirably long traces to place the bond pads serving as I/Os for the typical die in communication with the traces of the carrier substrate.
A related problem with the current techniques is the interconnectivity between dies. Signals that travel to other dies must traverse not just upwards in one die, but may also travel further upwards if the second die is on top of the first die. The signals may also traverse downward into a second die to reach the desired point on a given conduction layer in the second die. Thus, for example, the signal may traverse upwards through many conduction and dielectric layers to reach the top die surface and go through a ball, a bonding pad, or other connection structure on the first die. After a connection to a second die, the signal would then be similarly routed downwards from the top surface of, the second die to the desired layer in the second die. Thus, for example, a given signal could traverse about thirty-eight (fifty-four in the case of the 65 nm process of Texas Instruments) conduction and dielectric layers and their associated vias plus two conduction balls, bonding pads, or other connection structure. And, each of the contact layers adds resistance that, in combination with the total length traversed by the signals, may impact signal quality, speed, noise margin, bus skew, slack and setup/hold times, rise and fall times, potential spike generation and signal cancellation and makes timing convergence and other design and verification aspects difficult and sometimes limits upper clock frequencies.
Thus, such a tortured path impacts both speed and signal integrity. It is well known that interconnect delays are often much greater than gate delays below feature sizes of roughly 0.5 to 0.35 micron. Traversing substantial numbers of interconnect layers on two or more die considerably exacerbates the problems of timing convergence, layout, and architecture. Attempts to minimize these problems typically place restrictions on the layers regarding the manner in which signals can travel among these layers. These restrictions increase the already difficult layout and hinder designer creativity. They also sometimes force restrictions on the architecture of the chip.
Long path lengths also add significantly to the capacitance seen by the source and slow the signal down. Moreover, as line widths continually decrease, 22 nanometers currently in development, the number of “squares” and hence the resistance of the line in a given length of line increases by about the same factor as the decrease in line widths. This then increases the resistance seen by the driving source, again by about the same factor as the decrease of the line widths, all else being the same.
Furthermore, the increased line resistance adds to often already strained power usage and dissipation while making it more difficult to make bus signal elements and slave clock signals track their respective functions.
In addition, as higher speed IC assemblies operate at lower operational signal voltages, noise problems also become problematic. Mutual inductance results from an interaction between magnetic fields created by signal currents flowing to and from a packaged IC die through leads or traces, while self inductance results from the interaction of the foregoing fields with magnetic fields created by oppositely-directed currents flowing to and from ground. Signal propagation delays, switching noise, and crosstalk between signal conductors resulting from mutual and self inductance of the conductive paths contribute to signal degradation.
While lead inductance in IC packages has not traditionally been troublesome, the increasing signal frequencies of state-of-the-art electronic systems have substantially increased the practical significance of package lead or trace inductance. For example, at such faster signal frequencies, performance of IC die using extended leads or traces for external electrical connection is slower than desirable because the inductance associated with the elongated conductive paths required slows changes in signal currents through the leads or traces, prolonging signal propagation. In addition, digital signals propagating along the leads or traces are spreading out causing the signal components and signals themselves to disperse. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable. In addition, reflection signals propagating along the leads or traces as a result of impedance mismatches between the lead fingers and associated IC die or between the leads or traces and external circuitry, may distort normal signals propagating concurrently with the reflection signals. And, magnetic fields created by signal currents propagating through the lead or trace-associated inductance can induce currents in adjacent leads or traces, causing crosstalk noise.
Therefore, the state of the art die and package configurations described herein are having difficulties in keeping up with the trend towards faster devices at lower power. Noise problems are exacerbated by use of a large number of laterally adjacent traces of substantial and varying lengths extending from centralized die location to the horizontally-spaced, offset locations of vias extending to solder balls or other conductive elements for securing and electrically connecting the package to a carrier substrate.
There are various constraints that limit the number of signal traces that can be fabricated on a package. Industry standards impose specific requirements as to the spacing between solder balls, thereby restricting the spacing between the vias that electrically connect the signal traces to the solder bumps. The spacing restriction limits the number of signal traces that can fit between the vias which, in turn, limits the number of signal traces that can be used to carry signals to and from the die. Current fabrication technology imposes minimum pitch requirements for signal traces to attain satisfactory yields and to ensure mechanical and electrical reliability. The limitation on the maximum number of usable signal traces limits the maximum number of solder bumps, thereby placing a ceiling on the number of signals that a particular package can provide.
There are several levels of interconnections that make up an encapsulated integrated circuit. First, there are the internal interconnections of the circuit making up an individual die. Then there is the interconnection between the various dies themselves, especially if more than one die is in a package. There is also a connection layer between the dies and the package that allows external access.
With respect to the package connection, wire bonds are typically used to electrically connect the input/output (I/O) pads of the die to traces or pads on the package. If the die is on the side of the circuit board inside the package opposite the solder bumps, conductive vias are formed through the circuit to conduct signals from the solder bumps to the pads or traces. To enable routing in highly dense integrated circuit packages, there are many techniques known to those skilled in the art such as micro-vias, blind vias, buried vias, staggered vias.
A further problem with higher density and more complex circuit design relates to the verification at all the various steps along the process. As the number of layers and the die size increase, the resources to validate the different steps including the design rules of the layouts of the different layers increase exponentially.
In addition, the static power is greater due to leakage through the thin oxides required for the higher density circuits. There is also an increase in the number of conduction and concomitant dielectric layers which must be traversed to reach various parts of a given die and to interact with other dies. This increase gives rise to increased problems with layer to layer registration, step coverage with its potential failure modes, contact integrity, and validation problems. Because of aspect ratios, stepped vias must generally be used in most cases at the smaller feature sizes. However, using the stepped vias adds an additional mask layer for each such stepped via. Planarity also becomes more difficult with the denser circuits.
As noted herein, the existing packaging fail to address several criteria required for high density, high speed and low power packaging, namely: interconnections with non-planar die resulting from many layers on the die; limitations on the fanin/fanout; inability to monitor flip-chip packaging signals; and, very long signal travel paths resulting in signal reflection, degraded signal integrity, propagation delays, switching noise, crosstalk and dispersion. Therefore, what is needed is a mechanically and electrically desirable packaging scheme to accommodate high density high speed, low power packaging. Such a system should interconnect die without having to travel excessive paths and allow in-situ monitoring of critical signals. Ideally the system should be easily implemented without affecting the current and expected fabrication methods and machinery.